View Full Version : Have a look inside the v3.0
Hi there.
Might be interesting for someone. Here are some pictures from the inside of the Base3.0
http://codeq.de/HD_Base_all.jpg
upper left corner is the usb hub. 2 internal connectors. and 2 go to the outside. one on the side front and one at the back. All these share its bandwidth.
The usb connector below the Ethernet connector is directly connected to the mainboard which is the board at the bottom left.
2 S-ATA connectors are pressent. one is the external SATA (grey) at the back and one for the internal HDD (red).
the rest isnt really interesting. one analoug audio bridge and a power supply at the right.
the two wires (red and black) at the right corner on the mainboard are to unplug the fan if you desire.
the connector at the top right corner is for the frontpanel and the remote control.
the rest is for powering the stuff you see.
the chip id for the hynix memchip is unreadable here. would be nice to know whats inside. the small heat sink next to the SATA connectors covers the sigma chip.
http://codeq.de/HD_Base_main.jpg
installing some fast mem for better buffering behaviour would be great but without access to the os its obsolete to think about.
have fun
It's a Hynix HY27UF081G2A 1GB Memchip.
http://www.hynix.com/datasheet/pdf/flash/HY27UF(08_16)1G2A%20Series(Rev0.4).pdf
Description
The Hynix HY27UF(08/16)1G2A series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block.
Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input pin or using the extended lock block feature described later. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UF(08/16)1G2A extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out.
The HYNIX HY27UF(08/16)1G2A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP 12 x 17 mm.
Features
o
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
o
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
o
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27UFXX1G2A
o
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x1,024 Blocks
= (1K+32) Words x 64 pages x 1,024 Blocks
o
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UF081G2A
- x16 device: (1K + 32 spare) Bytes
: HY27UF161G2A
o
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
o
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
o
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
o
CACHE PROGRAM MODE
- Internal (2048+64)Byte buffer to improve the program throughput
o
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
o
STATUS REGISTER
o
ELECTRONIC SINGATURE
-1st cycle: Manufacture Code
- 2nd cycle: Device Doce
- 3rd cycle: Internal chip number, Cell Type, Number of Simultaneously Programmed Pages.
- 4th cycle: Page Size, Block Size, Oranization, Spare Size
o
SERIAL NUMBER OPTION
o
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
o
DATA INTEGRITY
-100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
o
PACKAGE
- HY27UF(08/16)1G2A-T(P)
:48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UF(08/16)1G2A-T (Lead)
- HY27UF(08/16)1G2A-TP (Lead Free)
- HY27UF(08/16)1G2A-S(P)
:48-Pin USOP1 (12 x17 x0.65 mm)
- HY27UF(08/16)1G2A-S (Lead)
- HY27UF(08/16)1G2A-SP (Lead Free)
Pics of the Prime 3 here: http://www.avsforum.com/avs-vb/showthread.php?t=1175778&page=16
Many thanks for this picture. For me putting this in a high-end system I'm mostly concerned about improving the power-supply. And I like that it seems pretty straightforward.
I have a question though. That fuse on the powersupply board, is that glued with blue glue? It's hard to see from the picture.
It looks like the fuse rating is T1.6AL/AC250V or is it T1.8AL/AC250V ?
The emtpy connector below the serialnumber on the mainboard is a serial connector. G(rnd) T(ransmit) R(eceive) V(cc).
I dont get anything readable so far. Looks like some TFPT stuff or a Commandline. I'll see tomorrow.
Many thanks for this picture. For me putting this in a high-end system I'm mostly concerned about improving the power-supply. And I like that it seems pretty straightforward.
I have a question though. That fuse on the powersupply board, is that glued with blue glue? It's hard to see from the picture.
It looks like the fuse rating is T1.6AL/AC250V or is it T1.8AL/AC250V ?
T1.8AL
and its glued.
Thanks for the inside view of the device..:)
Hi there.
Might be interesting for someone.
Yep, thanks!
the small heat sink next to the SATA connectors covers the sigma chip.
Are you sure? Haven't opened my prime yet, but me thinks this is the ethernet phy.
My guess is that the Sigma chip is located on the other side of the PCB. There's a dent/recess of the bottom plate, which acts as a chip cooler. It gets quite hot at this spot after a few ours of BD playing.
Cheers
Micael
Yep, thanks!
Are you sure? Haven't opened my prime yet, but me thinks this is the ethernet phy.
My guess is that the Sigma chip is located on the other side of the PCB. There's a dent/recess of the bottom plate, which acts as a chip cooler. It gets quite hot at this spot after a few ours of BD playing.
Cheers
Micael
You are right. The 8642 is at the back of the board. just read the white paper of the chip and the board layout. the 8642 is differently soldered than the one i pointed at.
Interesting whats included the chip and delivered with the SDK. Some problems we have here are bugs from the HDMI lib Sigma offers.
http://codeq.de/sigma_8642.JPG
Some problems we have here are bugs from the HDMI lib Sigma offers.
It's not really an "offer" for using the HDMI lib from Sigma.
This is forced onto the company's that use the board.
And i've heard a comment from HDI somewhere on this forum that this HDMI library is far from optimum. And unfortunately it's a closed source HDMI lib with no way to work around.
So if you want all HDMI problems to go away, don't bash on the company's that make the players. Bash on Sigma for delivering a buggy & closed library.
You are right. The 8642 is at the back of the board. just read the white paper of the chip and the board layout. the 8642 is differently soldered than the one i pointed at.
Confirmed, see pictures:
http://www.hdlandblog.com/2009/11/dune-bd-prime-30-test-review.html
http://1.bp.blogspot.com/_q4Fu6tvHesQ/SxFDTYz8toI/AAAAAAAAFMs/PwdB3GpHWM0/s1600/Dune-BD-Prime-3.0-motherboard.jpg
T1.8AL
and its glued.
In the BD Prime 3.0 it's an T1.6AL/250V and there is a clearblue plastic cover that you can remove and change the fuse if needed. I checked myself.
I have a rather odd request, can someone please take a close-up picture of the analog-board?
I am interested in what chip-types are used for DA-conversion, if they are of a suitable type we may have a prime candidate for being modded to a HiFi-nerds ultimate dream! ;)
Thanks in advance to anyone sharing !
*Bump* for a picture of the audio-DACs! ;)
ALL DA converters are good enough to drive any high end system these days.
It's the implementation of the DA conversion and OP amps that is critical...
But I agree, I would also like a high end version of the DUNE :rolleyes:
Someone had mentioned a pcie connector. ???
I would like to expand the sata capabilites.
Here are a few pictures:
Signals passed from Main Board to the audio DAC
http://www.lysator.liu.se/~jonma/HiFi/Equipment/Dune_BD_Prime_3_0/Audio-DAC-Signals_small.JPG (http://www.lysator.liu.se/~jonma/HiFi/Equipment/Dune_BD_Prime_3_0/Audio-DAC-Signals_med.JPG)
The top side of the audio DAC-board
http://www.lysator.liu.se/~jonma/HiFi/Equipment/Dune_BD_Prime_3_0/Topside_small.jpg (http://www.lysator.liu.se/~jonma/HiFi/Equipment/Dune_BD_Prime_3_0/Topside_med.jpg)
Presumably the Cirrus Logic CS4344 audio DAC and the AZ4580M-E1 Operational amplifier
http://www.lysator.liu.se/~jonma/HiFi/Equipment/Dune_BD_Prime_3_0/CS4344C%2bNJM4580M_small.jpg (http://www.lysator.liu.se/~jonma/HiFi/Equipment/Dune_BD_Prime_3_0/CS4344C%2bNJM4580M_small.jpg)
Edit, changed from NJM to AZ
Found the Datasheet from the opamps.
http://pdf1.alldatasheet.com/datasheet-pdf/view/176258/BCDSEMI/4580M-E1.html
Hello, i bought a few days ago a dune HD prime 3.0 without harddrive, works fine but now i see on the pictures that there is a fan build in. My player new from the box has no fan, is this right, and is there only a fan if sold with a harddrive?
thanks,
Peter
Hello, i bought a few days ago a dune HD prime 3.0 without harddrive, works fine but now i see on the pictures that there is a fan build in. My player new from the box has no fan, is this right, and is there only a fan if sold with a harddrive?
thanks,
Peter
the base has the fan build in by default. the prime only has the space to build in one by your own. it makes sence building in a fan if you want to use a harddrive. without hdd there is no fan needed. the same for the base. if you dont use an internal hdd then no fan is needed there aswell.
Is there someone who knows exactly what the specs are for the fuse on the PSU?
is there someone who knows exactly what the specs are for the fuse on the psu?
t1.6al/250v
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